1/8 AN1235 application note ? flip-chip: package description and recommendations for use march 2002 the competitive market of portable equipment, notably the mobile phone market, is driven by a challenging development of highly integrated products. to allow manufacturers of portable equipment to reduce the dimension of their products, stmicroelectronics has developped packages with reduced size, thickness and weight in the form of the flip-chip. the electrical performance of such components in flip-chip are improved thanks to shorter connections than the ones in standard plastic packages (as tssop, ssop or bga). this flip-chip package family has been designed to fulfill the same quality levels and the same reliability performances as standard semiconductor plastic packages. that means these new flip-chip packages have to be considered as new surface mount devices which will be assembled on a printed circuit board without any special or additionnal process steps required. in particular this package does not require any extra underfill to increase reliability performances or to protect the device. this package is reworkable and is compatible with existing pick and place equipment for board mounting. the purpose of this document is to describe the flip-chip features and to specify how our customers can use them. this application note addresses the following items : - product description - mechanical description - packing specifications and labelling description - recommended storage and shipping instructions - soldering assembly recommendations - user responsability and returns - changes - delivery quantity - quality i - introduction asd ? , ipad ?
application note 2/8 2.6 0.05 0.65 0.065 0.25 0.04 0.315 0.050 2.6 0.05 0.5 0.05 all dimensions in mm side and bottom views fig. 1: mechanical dimensions of a 5 x 5 bumps matrix array (sample) the flip-chips are manufactured with a wafer level process that stmicroelectronics has developed by attaching solder balls on i/os pads of the active wafer side, thus allowing bumped dice to be produced. the i/o contact layout can be either matrix shape or set in periphery. no redistribution layer is used. this allows parasitic inductances coming from the redistribution metal tracks to be minimized. the eutectic sn63pb37 bumps make this package compatible with standard reflow processes. the bumps' dimension (315 m m bumps diameter) allows the pick and place process to be compatible with existing equipment (in particular with equipment used for bga packages) and makes it also compatible with the pcb design rules used for standard ics. these components are delivered in tape&reel packing with the bumps turned down (placed on the bottom of the carrier tape cavity). the other face of the component is flat and allows picking as in the standard smd packages. devices are 100% electrically tested before packing. the product references are marked on the flat side of the device. ii - product description mechanical dimensions of flip-chips are provided through a product example in figure 1 below. bumps are in sn63pb37 alloy with an eutectic melting point of 183 c. die size and bump count are adapted to the connection requirements. iii - mechanical description note: the package height of 0.65mm is valid for a die thickness of 0.40mm. with a die thickness of 0.64mm the total height would be 0.89mm. the flip-chip tolerance on bumps diameter and bumps height are very narrow. this constant bumps shape insures a good coplanarity between bumps. optical measurements performed through vertical focuses show a bump plus die coplanarity below 80 m m. the product marking for both bumps side and top side is shown on figure 2 below (product example). the flip-chip has a pin marker (a1) on both the top and bottom sides so that the face of the component can be easily determined before and after assembly.the dots marked both on the top side and on the bumps side have been designed so that they can be detected by standard vision systems. marking dimensions are, of course, linked to the die size.
application note 3/8 product name top side 0.40 0.50 0.24 0.06 2.60 0.16 0.40 all dimensions in mm bumps side 0.120 0.10 oclear areao 0.120 a5 a4 a3 b1 c1 d1 e1 a1 a2 fig. 2: flip-chip marking example for a 5x5 bumps matrix array. st product name st product name st product name pin a1 location user direction of unreeling all dimensions in mm 4 +/- 0.1 8 +/- 0.3 4 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 1.5 +/- 0.1 fig. 3: layout of flip-chips in carrier tape (8mm carrier tape sample) the flip-chip products are delivered in tape & reel to be fully compatible with standard high volume smd components. the features of tape & reel materials are in accordance with eia-481-1, eia481-1-a and iec286-3 standards. all features not specified in this section are in accordance with eia-481-1, eia481-1-a and iec286-3 standards. iv.1 - carrier tape the flip-chips are placed in carrier tape with bumps side facing the bottom of the cavity so that the components can be picked-up by their top side. no flipping of the package is necessary for mounting on pcb. the products are positionned in the carrier tape with pin a1 nearest the round sprocket hole. carrier tape mechanical dimensions and flip-chip positionning is shown in figure 3 below. note : 12 mm carrier tape width may be used for a larger die size to be in line with eia standards. iv - packing specifications & labelling description
application note 4/8 the cavities in the carrier tape have been designed to avoid any damage to the components. no hole is present in the cavity in order to avoid any impact or any external contamination to the solder bumps. for flip-chips larger than 2 mm x 2 mm, the 8 mm width and 4 mm pitch carrier tape is designed to allow a maximum component tilt of 5 and a maximum lateral movement of 0.3 mm. the embossed carrier tape is in a black conductive material (surface resistivity within 10e4 and 10e8 ohm/square). conductivity is guaranteed to be constant and not affected by shelf life or humidity. the material will neither break when bent nor will rub off, powder, flake. the carrier tape tensile strength is higher than 40n. iv.2 - cover tape the carrier tape is sealed with a transparent, antistatic (surface resistivity within 10e5 ohm/square and 10e12 ohm/square) polyester film cover tape with a heat activated adhesive. the cover tape tensile strength is higher than 10n. the peeling force of the cover tape is between 0.1n and 0.7n by performing the testing method eia 481-1 and iec 286-3: cover tape is peeled back in the direction opposite to the carrier tape travel; the angle between the cover tape and the carrier tape is between 165 and 180 degrees and the test is done at a speed of 120 +/- 10 % mm/minute. iv.3 - reels the sealed carrier tape with the flip-chip is reeled on 7 inch reels (see figure 4 for reel mechanical dimensions). these reels are compliant with eia 481-1 standard. each reel contains 5000 components. in compliance with the iec286-3, each reel contains a maximum of 10 empty cavities with no more than 2 successive empty cavities. each reel may contain components coming from 2 different wafer lots. the reel is made of an antistatic polystyrene material. each reel has a minimum leader of 600 mm and a minimum trailer of 160 mm (compliant with eia 481-1 & iec 286-3 standards). the leader makes up a portion of carrier tape with empty cavities and sealed by cover tape at the beginning of the reel (external side). the leader is affixed to the last turn of the carrier tape by using adhesive tape. the trailer is at the end of the reel and consists of empty, sealed cavities. abcde fg 178 max 60 1 13 0.2 20.2 min 8.4 1.5 1.6 0.5 4 0.25 material: antistatic polystyrene all dimensions in mm e f g d a c b fig. 4: 7o reel mechanical dimensions
application note 5/8 iv.4 - final packing each reel is heat sealed under inert atmosphere in a transparent, recyclable and antistatic polyethylene bag (minimum of 4 mils material thickness). reels are then packed in cardboard boxes. the complete description for packing is shown on figure 5. 5000 components per reel reel in a sealed plastic bag inert atmosphere the reel is packed in a cardbox for storage & shipment fig. 5: packing flow chart iv.5 - labelling to ensure components' traceability, labels are stuck on the reels and the cardboard box. the seven inch reels and the cardboard box are identified by labels including part number, shipped quantity and traceability references (fig. 6). the traceability is ensured for each production lot and each shipment lot through the labeling. the qa number printed on the labels ensures backward traceability from the lot received by the customer to each step of the process: in / out dates and quantity at diffusion, assembly, test and final store. likewise, forward traceability is able to trace a lot history from the wafer fab to the customer's location. quantity stm part number qa number country of origin lot number fig. 6: example of a reel label
application note 6/4 flip-chip reels are packed under inert n2 atmosphere in a sealed bag. for shipment and handling, reels are packed in a cardboard box. stmicroelectronics thus recommends the following shipping and storage conditions : - relative humidity between 15% and 70% - temperature range from -5 cto35 c components in a non opened sealed bag can be stored 6 months after shipment. components in tape&reel must be protected from exposure to direct sunlight. moisture sensitivity level (msl as per jedec j-std-020a) is not applicable to flip-chip devices since there is no plastic encapsulation and so far no risk of moisture absorption and related possible package cracks. v- recommended storage, shipping instructions and descriptions vi.1 - pcb design recommendations for optimum electrical performance and highly reliable solder joints, stmicroelectronics recommends the pcb design guidelines listed in table 1. vi - soldering assembly recommendations pcb pad design non solder mask defined micro via under bump allowed pcb pad size ? = 300 m m max (circular) - 250 m m recommended solder mask opening ? = 340 m m min (for 300 m m diameter pad) pcb pad finishing cu - ni (2-6 m m) - au (0.2 m m max) table. 1: pcb design recommendations to optimize the natural self centering effect of flip-chips on pcb, pcb pad positioning and size have to be properly designed. note : a too thick gold layer finishing on the pcb pad is not recommended (low joint reliability). vi . 2 - pcb assembly guidelines for flip-chip mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 330 x 330 m m maximum and a typical stencil thickness of 125 m m. flip-chips are fully compatible with the use of eutectic sn63pb37 solder paste with no clean flux. st's recommendations for flip-chip board mounting are illustrated on the soldering reflow profile shown in figure 7.
application note 7/8 recommended:tpeak = 230 c &time above 183 c = 45 sec temperature ( c) 205 c min 250 c max 183 c 140 - 160 c 1 - 2 min 60 sec max time (min) 1to3 c/s 2to5 c/s 024 fig. 7: recommended soldering reflow profile for flip-chip mounting on pcb dwell time in the soldering zone (with temperature higher than 183 c) has to be kept as short as possible to prevent component and substrate damages. peak temperature must not exceed 250 c. controlled atmosphere (n2 or n2h2) is recommended during the whole reflow, specially above 150 c. flip-chips are able to withstand twice the previous recommended reflow profile in order to be compatible with a double reflow when smds are mounted on both sides of the pcb. a maximum of two soldering reflows are allowed for these packages. the use of a no clean flux is highly recommended to avoid any cleaning operation. in order to prevent any bump cracks, ultrasonic cleaning methods are not recommended. vi.3 - underfilling underfilling is not needed for flip-chips but the devices can withstand the dispense of an underfill if the process temperature does not exceed 175 c and if the process time is short (typically 5 minutes). vi.4 - manual rework flip-chips are able to tolerate one repair in addition to the two reflows mentionned in section vi.2. as for other bga type packages, the use of laser systems is the most suitable form for flip-chip repair. manual hot gas soldering is acceptable but iron soldering is not recommended. for manual rework, the maximum temperature allowed is 250 c and dwell time must not exceed 30 seconds. component replacement is preferred for such packages than manual rework. stmicroelectronics guarantees the excellent quality of its flip-chips in respect of the instructions provided in this application note. for more information, the reader can consult the asure 7o quality and reliability brochure. in the event that parts are found defective by the customer, the parts should be returned according to the st standard procedure within 60 days after the date of reception. vii - user responsability and returns
application note 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore spain - sweden - switzerland - united kingdom - united states. http://www.st.com flip-chip packages have been developped by stmicroelectronics for electronic applications where integration and performance are the main concerns of designers. stmicroelectronics flip-chips offer : - remarkable board space saving (package size equal to die size and total height less than 0.700mm) - enhanced electrical performance (minimized parasitic inductance due to very short electrical paths and absence of redistribution layer) - high reliability due to integration of a whole function traditionally based on discrete interconnected components. flip-chips are delivered in tape and reel and are fully compatible with other high volume smd components (standard plastic packages or csp/bga packages) regarding existing pick and place equipment, standard solder reflow assembly equipment and standard pcb techniques. x - conclusion ix.1 - electrical inspection products in flip-chip are 100% electrically probed according to the critical parameters of the st product specification. the last operation before packing is 100% electrical testing. the other parameters are guaranteed by technology, design rules and by continuous monitoring systems. ix.2 - visual inspection a visual control is performed on all manufacturing lots according to the mil-std-883 method 2010. ix - quality stmicroelectronics reserves the right to implement minor changes of geometry and manufacturing processes without prior notice. such changes will not affect electrical characteristics of the die, the pad layout or the maximum die size. however for confirmed orders, no variation will be made without customer's approval. viii - changes
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